forked from stm/stm32-mw-usb-device
220 lines
9.1 KiB
C
220 lines
9.1 KiB
C
/**
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******************************************************************************
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* @file usbd_ccid_cmd.h
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* @author MCD Application Team
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* @brief header file for the usbd_ccid_cmd.c file.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __USBD_CCID_CMD_H
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#define __USBD_CCID_CMD_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#ifndef __USBD_CCID_IF_H
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#include "usbd_ccid_if_template.h"
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#endif
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#ifndef __USBD_CCID_SC_IF_H
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#include "usbd_ccid_sc_if_template.h"
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#endif
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/* Exported types ------------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/******************************************************************************/
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/* ERROR CODES for USB Bulk In Messages : bError */
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/******************************************************************************/
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#define SLOT_NO_ERROR 0x81U
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#define SLOTERROR_UNKNOWN 0x82U
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/*----------------------------------------------------------------------------*/
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/* Index of not supported / incorrect message parameter : 7Fh to 01h */
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/* These Values are used for Return Types between Firmware Layers */
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/*
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Failure of a command
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The CCID cannot parse one parameter or the ICC is not supporting one parameter.
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Then the Slot Error register contains the index of the first bad parameter as a
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positive number (1-127). For instance, if the CCID receives an ICC command to
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an unimplemented slot, then the Slot Error register shall be set to 5 (index of bSlot field) */
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/* Following Parameters used in PC_to_RDR_XfrBlock */
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#define SLOTERROR_BAD_LENTGH 0x01U
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#define SLOTERROR_BAD_SLOT 0x05U
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#define SLOTERROR_BAD_POWERSELECT 0x07U
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#define SLOTERROR_BAD_PROTOCOLNUM 0x07U
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#define SLOTERROR_BAD_CLOCKCOMMAND 0x07U
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#define SLOTERROR_BAD_ABRFU_3B 0x07U
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#define SLOTERROR_BAD_BMCHANGES 0x07U
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#define SLOTERROR_BAD_BFUNCTION_MECHANICAL 0x07U
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#define SLOTERROR_BAD_ABRFU_2B 0x08U
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#define SLOTERROR_BAD_LEVELPARAMETER 0x08U
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#define SLOTERROR_BAD_FIDI 0x0AU
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#define SLOTERROR_BAD_T01CONVCHECKSUM 0x0BU
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#define SLOTERROR_BAD_GUARDTIME 0x0CU
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#define SLOTERROR_BAD_WAITINGINTEGER 0x0DU
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#define SLOTERROR_BAD_CLOCKSTOP 0x0EU
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#define SLOTERROR_BAD_IFSC 0x0FU
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#define SLOTERROR_BAD_NAD 0x10U
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#define SLOTERROR_BAD_DWLENGTH 0x08U
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/*---------- Table 6.2-2 Slot error register when bmCommandStatus = 1 */
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#define SLOTERROR_CMD_ABORTED 0xFFU
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#define SLOTERROR_ICC_MUTE 0xFEU
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#define SLOTERROR_XFR_PARITY_ERROR 0xFDU
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#define SLOTERROR_XFR_OVERRUN 0xFCU
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#define SLOTERROR_HW_ERROR 0xFBU
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#define SLOTERROR_BAD_ATR_TS 0xF8U
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#define SLOTERROR_BAD_ATR_TCK 0xF7U
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#define SLOTERROR_ICC_PROTOCOL_NOT_SUPPORTED 0xF6U
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#define SLOTERROR_ICC_CLASS_NOT_SUPPORTED 0xF5U
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#define SLOTERROR_PROCEDURE_BYTE_CONFLICT 0xF4U
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#define SLOTERROR_DEACTIVATED_PROTOCOL 0xF3U
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#define SLOTERROR_BUSY_WITH_AUTO_SEQUENCE 0xF2U
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#define SLOTERROR_PIN_TIMEOUT 0xF0U
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#define SLOTERROR_PIN_CANCELLED 0xEFU
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#define SLOTERROR_CMD_SLOT_BUSY 0xE0U
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#define SLOTERROR_CMD_NOT_SUPPORTED 0x00U
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/* Following Parameters used in PC_to_RDR_ResetParameters */
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/* DEFAULT_FIDI_VALUE */
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#ifndef DEFAULT_FIDI
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#define DEFAULT_FIDI 0x11U
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#endif
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#ifndef DEFAULT_T01CONVCHECKSUM
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#define DEFAULT_T01CONVCHECKSUM 0x00U
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#endif
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#ifndef DEFAULT_EXTRA_GUARDTIME
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#define DEFAULT_EXTRA_GUARDTIME 0x00U
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#endif
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#ifndef DEFAULT_WAITINGINTEGER
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#define DEFAULT_WAITINGINTEGER 0x0AU
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#endif
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#ifndef DEFAULT_CLOCKSTOP
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#define DEFAULT_CLOCKSTOP 0x00U
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#endif
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#ifndef DEFAULT_IFSC
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#define DEFAULT_IFSC 0x20U
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#endif
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#ifndef DEFAULT_NAD
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#define DEFAULT_NAD 0x00U
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#endif
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/* Following Parameters used in PC_to_RDR_IccPowerOn */
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#define VOLTAGE_SELECTION_AUTOMATIC 0xFFU
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#define VOLTAGE_SELECTION_3V 0x02U
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#define VOLTAGE_SELECTION_5V 0x01U
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#define VOLTAGE_SELECTION_1V8 0x03U
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/*
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Offset=0 bmICCStatus 2 bit 0, 1, 2
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0 - An ICC is present and active (power is on and stable, RST is inactive)
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1 - An ICC is present and inactive (not activated or shut down by hardware error)
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2 - No ICC is present
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3 - RFU
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Offset=0 bmRFU 4 bits 0 RFU
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Offset=6 bmCommandStatus 2 bits 0, 1, 2
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0 - Processed without error
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1 - Failed (error code provided by the error register)
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2 - Time Extension is requested
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3 - RFU
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*/
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#define BM_ICC_PRESENT_ACTIVE 0x00U
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#define BM_ICC_PRESENT_INACTIVE 0x01U
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#define BM_ICC_NO_ICC_PRESENT 0x02U
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#define BM_COMMAND_STATUS_OFFSET 0x06U
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#define BM_COMMAND_STATUS_NO_ERROR 0x00U
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#define BM_COMMAND_STATUS_FAILED (0x01U << BM_COMMAND_STATUS_OFFSET)
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#define BM_COMMAND_STATUS_TIME_EXTN (0x02 << BM_COMMAND_STATUS_OFFSET)
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#if (ATR_T01 == 0)
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#define SIZE_OF_ATR 19U
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#else
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#define SIZE_OF_ATR 15U
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#endif
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/* defines for the CCID_CMD Layers */
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#define LEN_RDR_TO_PC_SLOTSTATUS 10U
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#define LEN_PROTOCOL_STRUCT_T0 5U
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#define LEN_PROTOCOL_STRUCT_T1 7U
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#define BPROTOCOL_NUM_T0 0U
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#define BPROTOCOL_NUM_T1 1U
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/************************************************************************************/
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/* ERROR CODES for RDR_TO_PC_HARDWAREERROR Message : bHardwareErrorCode */
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/************************************************************************************/
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#define HARDWAREERRORCODE_OVERCURRENT 0x01U
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#define HARDWAREERRORCODE_VOLTAGEERROR 0x02U
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#define HARDWAREERRORCODE_OVERCURRENT_IT 0x04U
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#define HARDWAREERRORCODE_VOLTAGEERROR_IT 0x08U
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#define CHK_PARAM_SLOT 0x01U
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#define CHK_PARAM_DWLENGTH 0x02U
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#define CHK_PARAM_abRFU2 0x04U
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#define CHK_PARAM_abRFU3 0x08U
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#define CHK_PARAM_CARD_PRESENT 0x10U
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#define CHK_PARAM_ABORT 0x20U
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#define CHK_ACTIVE_STATE 0x40U
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/* Exported functions ------------------------------------------------------- */
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uint8_t PC_to_RDR_IccPowerOn(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_IccPowerOff(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_GetSlotStatus(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_XfrBlock(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_GetParameters(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_ResetParameters(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_SetParameters(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_Escape(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_IccClock(USBD_HandleTypeDef *pdev);
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uint8_t PC_to_RDR_Abort(USBD_HandleTypeDef *pdev);
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uint8_t PC_TO_RDR_T0Apdu(USBD_HandleTypeDef *pdev);
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uint8_t PC_TO_RDR_Mechanical(USBD_HandleTypeDef *pdev);
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uint8_t PC_TO_RDR_SetDataRateAndClockFrequency(USBD_HandleTypeDef *pdev);
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uint8_t PC_TO_RDR_Secure(USBD_HandleTypeDef *pdev);
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void RDR_to_PC_DataBlock(uint8_t errorCode, USBD_HandleTypeDef *pdev);
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void RDR_to_PC_NotifySlotChange(USBD_HandleTypeDef *pdev);
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void RDR_to_PC_SlotStatus(uint8_t errorCode, USBD_HandleTypeDef *pdev);
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void RDR_to_PC_Parameters(uint8_t errorCode, USBD_HandleTypeDef *pdev);
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void RDR_to_PC_Escape(uint8_t errorCode, USBD_HandleTypeDef *pdev);
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void RDR_to_PC_DataRateAndClockFrequency(uint8_t errorCode, USBD_HandleTypeDef *pdev);
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void CCID_UpdSlotStatus(USBD_HandleTypeDef *pdev, uint8_t slotStatus);
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void CCID_UpdSlotChange(USBD_HandleTypeDef *pdev, uint8_t changeStatus);
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uint8_t CCID_IsSlotStatusChange(USBD_HandleTypeDef *pdev);
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uint8_t CCID_CmdAbort(uint8_t slot, uint8_t seq);
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uint8_t USBD_CCID_Transfer_Data_Request(USBD_HandleTypeDef *pdev,
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uint8_t *dataPointer, uint16_t dataLen);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __USBD_CCID_CMD_H */
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